| Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture F Zhang, D Hwong, Y Sun, A Garcia, S Alhelaly, G Shofner, ... 2016 IEEE International Test Conference (ITC), 1-10, 2016 | 33 | 2016 |
| Repurposing FPGAs for tester design to enhance field-testing in a 3D stack Y Sun, F Zhang, H Jiang, K Nepal, J Dworak, T Manikas, RI Bahar Journal of Electronic Testing 35, 887-900, 2019 | 4 | 2019 |
| Test architecture for fine grained capture power reduction Y Sun, H Jiang, L Ramakrishnan, M Segal, K Nepal, J Dworak, T Manikas, ... 2019 26th IEEE International Conference on Electronics, Circuits and Systems …, 2019 | 4 | 2019 |
| Using existing reconfigurable logic in 3D die stacks for test F Zhang, Y Sun, X Shen, K Nepal, J Dworak, T Manikas, P Gui, RI Bahar, ... 2016 IEEE 25th North Atlantic Test Workshop (NATW), 46-52, 2016 | 4 | 2016 |
| Using a FPGA in a 3Dd Stacked IC to Prevent LSIB Bitstream Snooping Y Sun Southern Methodist University, 2015 | 4 | 2015 |
| Low power shift and capture through ATPG-configured embedded enable capture bits Y Sun, H Jiang, L Ramakrishnan, J Dworak, K Nepal, T Manikas, RI Bahar 2021 IEEE International Test Conference (ITC), 319-323, 2021 | 3 | 2021 |
| One more time! Increasing fault detection with scan shift capture H Jiang, F Zhang, Y Sun, J Dworak 2018 IEEE 27th North Atlantic Test Workshop (NATW), 1-7, 2018 | 2 | 2018 |
| Reducing Power During Manufacturing Test Using Different Architectures Y Sun | | 2021 |
