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Shinobu Nagayama
Shinobu Nagayama
Hiroshima City University
Verified email at hiroshima-cu.ac.jp - Homepage
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Cited by
Cited by
Year
Numerical function generators using LUT cascades
T Sasao, S Nagayama, JT Butler
IEEE Transactions on Computers 56 (6), 826-838, 2007
872007
Compact representations of logic functions using heterogeneous MDDs
S Nagayama, T Sasao
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 2003
582003
On the optimization of heterogeneous MDDs
S Nagayama, T Sasao
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005
572005
Minimization of average path length in BDDs by variable reordering
S Nagayama, A Mishchenko, T Sasao, JT Butler
NAVAL POSTGRADUATE SCHOOL MONTEREY CA DEPT OF ELECTRICAL AND COMPUTER …, 2003
332003
On the minimization of longest path length for decision diagrams
S Nagayama, T Sasao
Proc. of International Workshop on Logic and Synthesis, 28-35, 2004
272004
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method
S Nasayama, T Sasao, JT Butler
Asia and South Pacific Conference on Design Automation, 2006., 6 pp., 2006
252006
Complexities of graph-based representations for elementary functions
S Nagayama, T Sasao
IEEE Transactions on Computers 58 (1), 106-119, 2008
222008
Representations of elementary functions using edge-valued MDDs
S Nagayama, T Sasao
37th International Symposium on Multiple-Valued Logic (ISMVL'07), 5-5, 2007
222007
Code generation for embedded systems using heterogeneous MDDs
S Nagayama, T Sasao
the 12th workshop on Synthesis and System Integration of Mixed Information …, 2003
212003
Compact numerical function generators based on quadratic approximation: Architecture and synthesis method
S Nagayama, T Sasao, JT Butler
IEICE transactions on fundamentals of electronics, communications and …, 2006
192006
Representations of elementary functions using binary moment diagrams
T Sasao, S Nagayama
36th International Symposium on Multiple-Valued Logic (ISMVL'06), 28-28, 2006
182006
Analysis of multi-state systems with multi-state components using EVMDDs
S Nagayama, T Sasao, JT Butler
2012 IEEE 42nd International Symposium on Multiple-Valued Logic, 122-127, 2012
172012
A GPGPU implementation of approximate string matching with regular expression operators and comparison with its FPGA implementation
Y Utan, M Inagi, S Wakabayashi, S Nagayama
Proceedings of the International Conference on Parallel and Distributed …, 2012
162012
A systolic regular expression pattern matching engine and its application to network intrusion detection
Y Kawanaka, S Wakabayashi, S Nagayama
2008 International Conference on Field-Programmable Technology, 297-300, 2008
162008
Programmable numerical function generators: architectures and synthesis method
T Sasao, S Nagayama, JT Butler
International Conference on Field Programmable Logic and Applications, 2005 …, 2005
152005
Representations of logic functions using QRMDDs
S Nagayama, T Sasao, Y Iguchi, M Matsuura
Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic, 261-267, 2002
152002
An efficient heuristic for linear decomposition of index generation functions
S Nagayama, T Sasao, JT Butler
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL), 96-101, 2016
142016
Efficient FPGA-based hardware algorithms for approximate string matching
S Mikami, Y Kawanaka, S WAKABAYASHI, S Nagayama
ITC-CSCC: International Technical Conference on Circuits Systems, Computers …, 2008
142008
An efficient hardware matching engine for regular expression with nested Kleene operators
Y Wakaba, M Inagi, S Wakabayashi, S Nagayama
2011 21st International Conference on Field Programmable Logic and …, 2011
132011
Exact and heuristic minimization of the average path length in decision diagrams
S Nagayama, A Mishchenko, T Sasao, JT Butler
NAVAL POSTGRADUATE SCHOOL MONTEREY CA DEPT OF ELECTRICAL AND COMPUTER …, 2005
132005
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