| Domino logic designs for high-performance and leakage-tolerant applications F Moradi, TV Cao, EI Vatajelu, A Peiravi, H Mahmoodi, DT Wisland Integration 46 (3), 247-254, 2013 | 80 | 2013 |
| STT-MRAM-based PUF architecture exploiting magnetic tunnel junction fabrication-induced variability EI Vatajelu, GD Natale, M Barbareschi, L Torres, M Indaco, P Prinetto ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (1), 1-21, 2016 | 58 | 2016 |
| Nonvolatile memories: Present and future challenges EI Vatajelu, H Aziza, C Zambelli 2014 9th International Design and Test Symposium (IDT), 61-66, 2014 | 50 | 2014 |
| Challenges and solutions in emerging memory testing EI Vatajelu, P Prinetto, M Taouil, S Hamdioui IEEE Transactions on Emerging Topics in Computing 7 (3), 493-506, 2017 | 49 | 2017 |
| Special session: Reliability of hardware-implemented spiking neural networks (SNN) EI Vatajelu, G Di Natale, L Anghel 2019 IEEE 37th VLSI Test Symposium (VTS), 1-8, 2019 | 38 | 2019 |
| Towards a highly reliable SRAM-based PUFs EI Vatajelu, G Di Natale, P Prinetto 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 273-276, 2016 | 35 | 2016 |
| High-entropy stt-MTJ-based TRNG EI Vatajelu, G Di Natale IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (2), 491-495, 2018 | 33 | 2018 |
| Test and reliability in approximate computing L Anghel, M Benabdenbi, A Bosio, M Traiola, EI Vatajelu Journal of Electronic Testing 34 (4), 375-387, 2018 | 31 | 2018 |
| Stt mram-based pufs EI Vatajelu, G Di Natale, M Indaco, P Prinetto 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 872-875, 2015 | 27 | 2015 |
| On the encryption of the challenge in physically unclonable functions EI Vatajelu, G Di Natale, MS Mispan, B Halak 2019 IEEE 25th International Symposium on On-Line Testing and Robust System …, 2019 | 22 | 2019 |
| Security primitives (puf and trng) with stt-mram EI Vatajelu, G Di Natale, P Prinetto 2016 IEEE 34th VLSI Test Symposium (VTS), 1-4, 2016 | 22 | 2016 |
| Statistical analysis of 6T SRAM data retention voltage under process variation EI Vatajelu, J Figueras 14th IEEE International Symposium on Design and Diagnostics of Electronic …, 2011 | 22 | 2011 |
| Supply voltage reduction in SRAMs: Impact on static noise margins EI Vatajelu, J Figueras 2008 IEEE international conference on automation, quality and testing …, 2008 | 20 | 2008 |
| Machine learning and hardware security: Challenges and opportunities F Regazzoni, S Bhasin, AA Pour, I Alshaer, F Aydin, A Aysu, V Beroulle, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-6, 2020 | 18 | 2020 |
| Process variability in sub-16nm bulk CMOS technology A Rubio, J Figueras, EI Vatajelu, R Canal Project: Terascale Reliable Adaptive Memory Systems, FP7-INFSO–IST-248789 12, 2012 | 17 | 2012 |
| Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis EI Vatajelu, G Panagopoulos, K Roy, J Figueras 2010 15th IEEE European Test Symposium, 69-74, 2010 | 17 | 2010 |
| State of the art and challenges for test and reliability of emerging nonvolatile resistive memories EI Vatajelu, P Pouyan, S Hamdioui International Journal of Circuit Theory and Applications 46 (1), 4-28, 2018 | 15 | 2018 |
| STT-MTJ-based TRNG with on-the-fly temperature/current variation compensation EI Vatajelu, G Di Natale, P Prinetto 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System …, 2016 | 15 | 2016 |
| Robustness analysis of 6T SRAMs in memory retention mode under PVT variations EI Vatajelu, J Figueras 2011 Design, Automation & Test in Europe, 1-6, 2011 | 15 | 2011 |
| Fully-connected single-layer stt-mtj-based spiking neural network under process variability EI Vatajelu, L Anghel 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2017 | 14 | 2017 |
