Farimah Farahmandi
Farimah Farahmandi
Assistant Professor, University of Florida
Verified email at - Homepage
Cited by
Cited by
Pre-silicon security verification and validation: A formal perspective
X Guo, RG Dutta, Y Jin, F Farahmandi, P Mishra
Proceedings of the 52nd annual design automation conference, 1-6, 2015
Defense-in-depth: A recipe for logic locking to prevail
MT Rahman, MS Rahman, H Wang, S Tajik, W Khalil, F Farahmandi, ...
Integration 72, 39-57, 2020
Hardware Trojan detection using ATPG and model checking
J Cruz, F Farahmandi, A Ahmed, P Mishra
2018 31st international conference on VLSI design and 2018 17th …, 2018
Trojan localization using symbolic algebra
F Farahmandi, Y Huang, P Mishra
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 591-597, 2017
System-on-chip security
F Farahmandi, Y Huang, P Mishra
Springer, 2020
Gröbner basis based formal verification of large arithmetic circuits using gaussian elimination and cone-based polynomial extraction
F Farahmandi, B Alizadeh
Microprocessors and Microsystems 39 (2), 83-96, 2015
Security-aware FSM design flow for identifying and mitigating vulnerabilities to fault attacks
A Nahiyan, F Farahmandi, P Mishra, D Forte, M Tehranipoor
IEEE Transactions on Computer-aided design of integrated circuits and …, 2018
Advances in logic locking: Past, present, and prospects
HM Kamali, KZ Azar, F Farahmandi, M Tehranipoor
Cryptology ePrint Archive, 2022
Scalable hardware trojan activation by interleaving concrete simulation and symbolic execution
A Ahmed, F Farahmandi, Y Iskander, P Mishra
2018 IEEE International Test Conference (ITC), 1-10, 2018
Directed test generation using concolic testing on RTL models
A Ahmed, F Farahmandi, P Mishra
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
Automated Test Generation for Debugging Arithmetic Circuits
F Farahmandi, P Mishra
Design Automation and Test in Europe (DATE), 2016
Soc security verification using property checking
N Farzana, F Rahman, M Tehranipoor, F Farahmandi
2019 IEEE International Test Conference (ITC), 1-10, 2019
Sofi: Security property-driven vulnerability assessments of ics against fault-injection attacks
H Wang, H Li, F Rahman, MM Tehranipoor, F Farahmandi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021
Script: A cad framework for power side-channel vulnerability assessment using information flow tracking and pattern generation
A Nahiyan, J Park, M He, Y Iskander, F Farahmandi, D Forte, ...
ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (3 …, 2020
Security assessment of dynamically obfuscated scan chain against oracle-guided attacks
MS Rahman, A Nahiyan, F Rahman, S Fazzari, K Plaks, F Farahmandi, ...
ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (4 …, 2021
Automated test generation for debugging multiple bugs in arithmetic circuits
F Farahmandi, P Mishra
IEEE Transactions on Computers 68 (2), 182-197, 2018
Post-Silicon Validation and Debug
P Mishra, F Farahmandi
Springer International Publishing, 2019
Cost-effective analysis of post-silicon functional coverage events
F Farahmandi, R Morad, A Ziv, Z Nevo, P Mishra
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
FPGA bitstream security: a day in the life
A Duncan, F Rahman, A Lukefahr, F Farahmandi, M Tehranipoor
2019 IEEE International Test Conference (ITC), 1-10, 2019
Automated debugging of arithmetic circuits using incremental gröbner basis reduction
F Farahmandi, P Mishra
2017 IEEE International Conference on Computer Design (ICCD), 193-200, 2017
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