| Coscale: Coordinating cpu and memory system dvfs in server systems Q Deng, D Meisner, A Bhattacharjee, TF Wenisch, R Bianchini 2012 45th annual IEEE/ACM international symposium on microarchitecture, 143-154, 2012 | 255 | 2012 |
| Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors A Bhattacharjee, M Martonosi ACM SIGARCH Computer Architecture News 37 (3), 290-301, 2009 | 237 | 2009 |
| Colt: Coalesced large-reach tlbs B Pham, V Vaidyanathan, A Jaleel, A Bhattacharjee 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 258-269, 2012 | 211 | 2012 |
| Architectural Support for Address Translation on GPUs B Pichai, L Hsu, A Bhattacharjee | 186* | 2014 |
| Shared last-level TLBs for chip multiprocessors A Bhattacharjee, D Lustig, M Martonosi 2011 IEEE 17th International Symposium on High Performance Computer …, 2011 | 179 | 2011 |
| Increasing TLB reach by exploiting clustering in page translations B Pham, A Bhattacharjee, Y Eckert, GH Loh 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 161 | 2014 |
| Large-reach memory management unit caches A Bhattacharjee Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 159 | 2013 |
| Inter-core cooperative TLB for chip multiprocessors A Bhattacharjee, M Martonosi ACM Sigplan Notices 45 (3), 359-370, 2010 | 148 | 2010 |
| Characterizing the TLB behavior of emerging parallel workloads on chip multiprocessors A Bhattacharjee, M Martonosi 2009 18th International Conference on Parallel Architectures and Compilation …, 2009 | 128 | 2009 |
| Efficient address translation for architectures with multiple page sizes G Cox, A Bhattacharjee ACM SIGPLAN Notices 52 (4), 435-448, 2017 | 116 | 2017 |
| Large pages and lightweight memory management in virtualized environments: Can you have it both ways? B Pham, J Veselŭ, GH Loh, A Bhattacharjee Proceedings of the 48th International Symposium on Microarchitecture, 1-12, 2015 | 113 | 2015 |
| Observations and opportunities in architecting shared virtual memory for heterogeneous systems J Vesely, A Basu, M Oskin, GH Loh, A Bhattacharjee 2016 IEEE International Symposium on Performance Analysis of Systems and …, 2016 | 106 | 2016 |
| MultiScale: memory system DVFS with multiple memory controllers Q Deng, D Meisner, A Bhattacharjee, TF Wenisch, R Bianchini Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012 | 100 | 2012 |
| Nimble page management for tiered memory systems Z Yan, D Lustig, D Nellans, A Bhattacharjee Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019 | 91 | 2019 |
| TLB improvements for chip multiprocessors: Inter-core cooperative prefetchers and shared last-level TLBs D Lustig, A Bhattacharjee, M Martonosi ACM Transactions on Architecture and Code Optimization (TACO) 10 (1), 1-38, 2013 | 88 | 2013 |
| Translation-triggered prefetching A Bhattacharjee Proceedings of the Twenty-Second International Conference on Architectural …, 2017 | 65 | 2017 |
| Full-system chip multiprocessor power evaluations using FPGA-based emulation A Bhattacharjee, G Contreras, M Martonosi Proceedings of the 2008 international symposium on Low Power Electronics …, 2008 | 64 | 2008 |
| Scheduling page table walks for irregular GPU applications S Shin, G Cox, M Oskin, GH Loh, Y Solihin, A Bhattacharjee, A Basu 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 57 | 2018 |
| COATCheck: Verifying memory ordering at the hardware-OS interface D Lustig, G Sethi, M Martonosi, A Bhattacharjee ACM SIGPLAN Notices 51 (4), 233-247, 2016 | 55 | 2016 |
| LATR: Lazy translation coherence MK Kumar, S Maass, S Kashyap, J Veselŭ, Z Yan, T Kim, A Bhattacharjee, ... Proceedings of the Twenty-Third International Conference on Architectural …, 2018 | 45 | 2018 |
Margaret MartonosiProfessor of Computer Science, Princeton UniversityVerified email at princeton.edu
