| A novel high-speed and energy efficient 10-transistor full adder design JF Lin, YT Hwang, MH Sheu, CC Ho IEEE Transactions on Circuits and Systems I: Regular Papers 54 (5), 1050-1059, 2007 | 307 | 2007 |
| Low-power pulse-triggered flip-flop design with conditional pulse-enhancement scheme YT Hwang, JF Lin, MH Sheu IEEE transactions on very large scale integration (VLSI) systems 20 (2), 361-366, 2011 | 129 | 2011 |
| High-speed, low-complexity systolic designs of novel iterative division algorithms in GF (2/sup m/) CH Wu, CM Wu, MD Shieh, YT Hwang IEEE Transactions on Computers 53 (3), 375-380, 2004 | 75 | 2004 |
| Low-power 19-transistor true single-phase clocking flip-flop design based on logic structure reduction schemes JF Lin, MH Sheu, YT Hwang, CS Wong, MY Tsai IEEE transactions on very large scale integration (VLSI) systems 25 (11 …, 2017 | 70 | 2017 |
| An efficient lossless compression scheme for hyperspectral images using two-stage prediction CC Lin, YT Hwang IEEE Geoscience and Remote Sensing Letters 7 (3), 558-562, 2010 | 62 | 2010 |
| Low voltage and low power divide-by-2/3 counter design using pass transistor logic circuit technique YT Hwang, JF Lin IEEE transactions on very large scale integration (vlsi) systems 20 (9 …, 2011 | 47 | 2011 |
| A low complexity complex QR factorization design for signal detection in MIMO OFDM systems YT Hwang, WD Chen 2008 IEEE International Symposium on Circuits and Systems (ISCAS), 932-935, 2008 | 39 | 2008 |
| Systolic VLSI realization of a novel iterative division algorithm over GF (2/sup m/): a high-speed, low-complexity design CH Wu, CM Wu, MD Shieh, YT Hwang ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems …, 2001 | 33 | 2001 |
| Low power 10-transistor full adder design based on degenerate pass transistor logic JF Lin, YT Hwang, MH Sheu 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 496-499, 2012 | 32 | 2012 |
| Single‐ended structure sense‐amplifier‐based flip‐flop for low‐power systems JF Lin, YT Hwang, CS Wong, MH Sheu Electronics Letters 51 (1), 20-21, 2015 | 27 | 2015 |
| Lossless hyperspectral image compression system-based on HW/SW codesign YT Hwang, CC Lin, RT Hung IEEE Embedded Systems Letters 3 (1), 20-23, 2010 | 26 | 2010 |
| VLSI architectural design tradeoffs for sliding-window log-MAP decoders CM Wu, MD Shieh, CH Wu, YT Hwang, JH Chen IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (4), 439-447, 2005 | 26 | 2005 |
| The embedded software consortium of Taiwan TY Huang, CT King, YLS Lin, YT Hwang ACM Transactions on Embedded Computing Systems (TECS) 4 (3), 612-632, 2005 | 25 | 2005 |
| Lossless Compression of Hyperspectral Images Using Adaptive Prediction and Backward Search Schemes. CC Lin, YT Hwang J. Inf. Sci. Eng. 27 (2), 419-435, 2011 | 23 | 2011 |
| An efficient shape coding scheme and its codec design YT Hwang, YC Wang, SS Wang 2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and …, 2001 | 22 | 2001 |
| MSSM—A design aid for multi-stage systolic mapping YT Hwang, YH Hu Journal of VLSI signal processing systems for signal, image and video …, 1992 | 22 | 1992 |
| Low-complexity high-throughput QR decomposition design for MIMO systems JS Lin, YT Hwang, SH Fang, PH Chu, MD Shieh IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (10 …, 2014 | 21 | 2014 |
| A low-complexity embedded compression codec design with rate control for high-definition video YT Hwang, MW Lyu, CC Lin IEEE Transactions on Circuits and Systems for Video Technology 25 (4), 674-687, 2014 | 20 | 2014 |
| Real-time FPGA-based template matching module for visual inspection application JY Chen, KF Hung, HY Lin, YC Chang, YT Hwang, CK Yu, CR Hong, ... 2012 IEEE/ASME International Conference on Advanced Intelligent Mechatronics …, 2012 | 20 | 2012 |
| A high-speed network interface design for packet-based NoC YL Lai, SW Yang, MH Sheu, YT Hwang, HY Tang, PZ Huang 2006 International Conference on Communications, Circuits and Systems 4 …, 2006 | 20 | 2006 |
