| A model for transient fault propagation in combinatorial logic M Omana, G Papasso, D Rossi, C Metra 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., 111-115, 2003 | 177 | 2003 |
| Latch susceptibility to transient faults and new hardening approach M Omana, D Rossi, C Metra IEEE Transactions on Computers 56 (9), 1255-1268, 2007 | 164 | 2007 |
| High-performance robust latches M Omaña, D Rossi, C Metra IEEE Transactions on Computers 59 (11), 1455-1465, 2010 | 113 | 2010 |
| Modeling crosstalk effects in CNT bus architectures D Rossi, JM Cazeaux, C Metra, F Lombardi IEEE Transactions on Nanotechnology 6 (2), 133-145, 2007 | 112 | 2007 |
| Multiple transient faults in logic: An issue for next generation ICs? D Rossi, M Omana, F Toma, C Metra 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2005 | 110 | 2005 |
| Novel Transient Fault Hardened Static Latch. M Omana, D Rossi, C Metra ITC, 886-892, 2003 | 95 | 2003 |
| Exploiting ECC redundancy to minimize crosstalk impact D Rossi, C Metra, AK Nieuwland, A Katoch IEEE Design & Test of Computers 22 (1), 59-70, 2005 | 93 | 2005 |
| Configurable error control scheme for NoC signal integrity D Rossi, P Angelini, C Metra 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 43-48, 2007 | 85 | 2007 |
| Modeling and detection of hotspot in shaded photovoltaic cells D Rossi, M Omaña, D Giaffreda, C Metra IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (6 …, 2014 | 72 | 2014 |
| New ECC for crosstalk impact minimization D Rossi, C Metra, AK Nieuwland, A Katoch IEEE design & test of computers 22 (4), 340-348, 2005 | 67 | 2005 |
| On transistor level gate sizing for increased robustness to transient faults JM Cazeaux, D Rossi, M Omaña, C Metra, A Chatterjee 11th IEEE International On-Line Testing Symposium, 23-28, 2005 | 65 | 2005 |
| Error correcting code analysis for cache memory high reliability and performance D Rossi, N Timoncini, M Spica, C Metra 2011 Design, Automation & Test in Europe, 1-6, 2011 | 61 | 2011 |
| Low Cost NBTI Degradation Detection & Masking Approaches M Omana, D Rossi, N Bosio, C Metra IEEE Transactions on Computers 62 (3), 496-509, 2013 | 57 | 2013 |
| Impact of aging phenomena on soft error susceptibility D Rossi, M Omaña, C Metra, A Paccagnella 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2011 | 43 | 2011 |
| Accurate linear model for SET critical charge estimation D Rossi, JM Cazeaux, M Omana, C Metra, A Chatterjee IEEE transactions on very large scale integration (VLSI) systems 17 (8 …, 2009 | 43 | 2009 |
| Coding scheme for low energy consumption fault-tolerant bus D Rossi, VES Van Dijk, RP Kleihorst, AH Nieuwland, C Metra Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW …, 2002 | 42 | 2002 |
| New high speed CMOS self-checking voter JM Cazeaux, D Rossi, C Metra Proceedings. 10th IEEE International On-Line Testing Symposium, 58-63, 2004 | 40 | 2004 |
| Power consumption of fault tolerant busses D Rossi, AK Nieuwland, SVES Van Dijk, RP Kleihorst, C Metra IEEE transactions on very large scale integration (VLSI) systems 16 (5), 542-553, 2008 | 39 | 2008 |
| Aging benefits in nanometer CMOS designs D Rossi, V Tenentes, S Yang, S Khursheed, BM Al-Hashimi IEEE Transactions on Circuits and Systems II: Express Briefs 64 (3), 324-328, 2016 | 38 | 2016 |
| Impact of Bias Temperature Instability on Soft Error Susceptibility D Rossi, M Omaña, C Metra, A Paccagnella IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (4), 743 …, 2015 | 38 | 2015 |
Vasileios TenentesAssistant Professor of Computer Science and Engineering, University of IoanninaBekræftet mail på arm.com
