| Designing 2D and 3D network-on-chip architectures K Tatas, K Siozios, D Soudris, A Jantsch Springer, 2014 | 118 | 2014 |
| Reliable IoT-based monitoring and control of hydroponic systems K Tatas, A Al-Zoubi, N Christofides, C Zannettis, M Chrysostomou, ... Technologies 10 (1), 26, 2022 | 53 | 2022 |
| Data-reuse and parallel embedded architectures for low-power, real-time multimedia applications D Soudris, ND Zervas, A Argyriou, M Dasygenis, K Tatas, CE Goutis, ... Integrated Circuit Design: Power and Timing Modeling, Optimization and …, 2000 | 51 | 2000 |
| DAGGER: A novel generic methodology for FPGA bitstream generation and its software tool implementation K Siozios, G Koutroumpezis, K Tatas, D Soudris, A Thanailakis 19th IEEE International Parallel and Distributed Processing Symposium, 4 pp., 2005 | 30 | 2005 |
| An integrated framework for architecture level exploration of reconfigurable platform K Siozios, K Tatas, G Koutroumpezis, D Soudris, A Thanailakis International Conference on Field Programmable Logic and Applications, 2005 …, 2005 | 21 | 2005 |
| iponics: Iot monitoring and control for hydroponics K Tatas, A Al-Zoubi, A Antoniou, D Zolotareva 2021 10th International Conference on Modern Circuits and Systems …, 2021 | 16 | 2021 |
| A survey of existing fine-grain reconfigurable architectures and CAD tools K Tatas, K Siozios, D Soudris Fine-and Coarse-Grain Reconfigurable Computing, 3-87, 2007 | 16 | 2007 |
| A novel FPGA architecture and an integrated framework of CAD tools for implementing applications K Siozios, G Koutroumpezis, K Tatas, N Vassiliadis, V Kalenteridis, ... IEICE transactions on information and systems 88 (7), 1369-1380, 2005 | 16 | 2005 |
| An integrated FPGA design framework: Custom designed FPGA platform and application mapping toolset development V Kalenteridis, H Pournara, K Siozios, K Tatas, G Koytroympezis, ... 18th International Parallel and Distributed Processing Symposium, 2004 …, 2004 | 16 | 2004 |
| Power and performance exploration of embedded systems executing multimedia kernels M Dasygenis, N Kroupis, K Tatas, A Argyriou, D Soudris, A Thanailakis IEE Proceedings-Computers and Digital Techniques 149 (4), 164-172, 2002 | 16 | 2002 |
| Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications K Tatas, G Koutroumpezis, D Soudris, A Thanailakis Integration 40 (2), 74-93, 2007 | 15 | 2007 |
| FPGA architecture design and toolset for logic implementation K Tatas, K Siozios, N Vasiliadis, DJ Soudris, S Nikolaidis, S Siskos, ... Integrated Circuit and System Design. Power and Timing Modeling …, 2003 | 14 | 2003 |
| A memory management approach for efficient implementation of multimedia kernels on programmable architectures M Dasigenis, N Kroupis, A Argyriou, K Tatas, D Soudris, A Thanailakis, ... Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging …, 2001 | 14 | 2001 |
| A complete platform and toolset for system implementation on fine-grain reconfigurable hardware V Kalenteridis, H Pournara, K Siozos, K Tatas, N Vassiliadis, I Pappas, ... Microprocessors and Microsystems 29 (6), 247-259, 2005 | 12 | 2005 |
| A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems D Soudris, K Sgouropoulos, K Tatas, V Pavlidis, A Thanailakis Proceedings of the 2003 International Symposium on Circuits and Systems …, 2003 | 12 | 2003 |
| A novel division algorithm for parallel and sequential processing K Tatas, DJ Soudris, D Siomos, M Dasygenis, A Thanailakis 9th International Conference on Electronics, Circuits and Systems 2, 553-556, 2002 | 12 | 2002 |
| A full adder based methodology for scaling operation in residue number system D Soudris, M Dasygenis, K Mitroglou, K Tatas, A Thanailakis 9th International Conference on Electronics, Circuits and Systems 3, 891-894, 2002 | 12 | 2002 |
| A novel FPGA configuration bitstream generation algorithm and tool development K Siozios, G Koutroumpezis, K Tatas, D Soudris, A Thanailakis Field Programmable Logic and Application: 14th International Conference, FPL …, 2004 | 11 | 2004 |
| Hardware implementation of dynamic fuzzy logic based routing in Network-on-Chip K Tatas, C Chrysostomou Microprocessors and Microsystems 52, 80-88, 2017 | 10 | 2017 |
| 3DBUFFBLESS: A novel buffered-bufferless hybrid router for 3D networks-on-chip K Tatas, S Savva, C Kyriacou 2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017 | 9 | 2017 |
