| An overview of through-silicon-via technology and manufacturing challenges JP Gambino, SA Adderly, JU Knickerbocker Microelectronic Engineering 135, 73-106, 2015 | 260 | 2015 |
| Electric vehicles and natural disaster policy implications SA Adderly, D Manukian, TD Sullivan, M Son Energy Policy 112, 437-448, 2018 | 69 | 2018 |
| Anticipatorily loading a page of memory SA Adderly, PA Niekrewicz, A Suren, ST Ventrone US Patent 9,201,806, 2015 | 10 | 2015 |
| Reviewing power outage trends, electric reliability indices and smart grid funding S Adderly The University of Vermont and State Agricultural College, 2016 | 9 | 2016 |
| Apparatus and method for centering substrates on a chuck SA Adderly, SD DiStefano, JP Gambino, MG Levy, ML Lifson, MD Moon, ... US Patent 9,685,362, 2017 | 8 | 2017 |
| Centering substrates on a chuck SA Adderly, SD DiStefano, JP Gambino, MG Levy, ML Lifson, MD Moon, ... US Patent 10,224,225, 2019 | 7 | 2019 |
| Nano deposition and ablation for the repair and fabrication of integrated circuits SA Adderly, JP Gambino, EA Joseph, AC Speranza US Patent 9,583,401, 2017 | 7 | 2017 |
| Method and apparatus for detecting foreign material on a chuck SA Adderly, SD DiStefano, JP Gambino, MG Levy, ML Lifson, JH Rankin, ... US Patent 9,508,578, 2016 | 6 | 2016 |
| Imaging of through-silicon vias using X-Ray computed tomography JP Gambino, W Bowe, DM Bronson, SA Adderly Proceedings of the 21th International Symposium on the Physical and Failure …, 2014 | 6 | 2014 |
| Evaluating the potential impact of smart grid funding on reducing the economic impact of large outage events in the United States from 2003 to 2017 S Adderly, T Peterson, D Manukian, T Sullivan, M Son, R Mickey Technology and Economics of Smart Grids and Sustainable Energy 4, 1-10, 2019 | 5 | 2019 |
| Uniform roughness on backside of a wafer SA Adderly, JP Gambino, ML Lifson, MD Moon, WJ Murphy, TD Sullivan, ... US Patent 9,275,868, 2016 | 5 | 2016 |
| Method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof SA Adderly, BM Czabaj, DA Delibac, JP Gambino, MD Moon, DC Thomas US Patent 9,006,703, 2015 | 5 | 2015 |
| Nano deposition and ablation for the repair and fabrication of integrated circuits SA Adderly, JP Gambino, EA Joseph, AC Speranza US Patent 10,607,899, 2020 | 2 | 2020 |
| Void monitoring device for measurement of wafer temperature variations SA Adderly, SD DiStefano, MJ Esposito, JP Gambino, P Periasamy US Patent 9,543,219, 2017 | 2 | 2017 |
| Centering substrates on a chuck SA Adderly, SD DiStefano, JP Gambino, MG Levy, ML Lifson, MD Moon, ... US Patent 9,997,385, 2018 | 1 | 2018 |
| Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside roughness SA Adderly, K Babinski, DA Delibac, DA DeMuynck, SR Goddard, ... US Patent 9,330,988, 2016 | 1 | 2016 |
| Achieving uniform capacitance between an electrostatic chuck and a semiconductor wafer SA Adderly, JP Gambino, WJ Murphy, JD Chapple-Sokol US Patent 9,196,519, 2015 | 1 | 2015 |
| The effect of backside roughness on Al interconnect dimensions for RF CMOS SOI devices MD Moon, JP Gambino, SA Adderly, J Hanrahan, B Cucci 25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014 …, 2014 | 1 | 2014 |
| The effect of etch residuals on via reliability SA Adderly, MD Moon, ML Lifson, NW Bowe, JP Gambino, TD Sullivan 2013 IEEE Conference on Reliability Science for Advanced Materials and …, 2013 | 1 | 2013 |
| Waveguide structures used in phonotics chip packaging SA Adderly, SD DiStefano, JP Gambino, P Periasamy, DR Letourneau US Patent 10,078,183, 2018 | | 2018 |
Jeffrey GambinoIBMVerificeret mail på us.ibm.com
