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Adib Nahiyan
Adib Nahiyan
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Title
Cited by
Cited by
Year
AVFSM: A framework for identifying and mitigating vulnerabilities in FSMs
A Nahiyan, K Xiao, K Yang, Y Jin, D Forte, M Tehranipoor
Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016
1182016
Security-aware FSM design flow for identifying and mitigating vulnerabilities to fault attacks
A Nahiyan, F Farahmandi, P Mishra, D Forte, M Tehranipoor
IEEE Transactions on Computer-aided design of integrated circuits and …, 2018
572018
RTL-PSC: Automated power side-channel leakage assessment at register-transfer level
M He, J Park, A Nahiyan, A Vassilev, Y Jin, M Tehranipoor
2019 IEEE 37th VLSI Test Symposium (VTS), 1-6, 2019
562019
Hardware trojan detection through information flow security verification
A Nahiyan, M Sadi, R Vittal, G Contreras, D Forte, M Tehranipoor
2017 IEEE International Test Conference (ITC), 1-10, 2017
542017
Security vulnerability analysis of design-for-test exploits for asset protection in SoCs
GK Contreras, A Nahiyan, S Bhunia, D Forte, M Tehranipoor
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 617-622, 2017
472017
A physical design flow against front-side probing attacks by internal shielding
H Wang, Q Shi, A Nahiyan, D Forte, MM Tehranipoor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
352019
Script: A cad framework for power side-channel vulnerability assessment using information flow tracking and pattern generation
A Nahiyan, J Park, M He, Y Iskander, F Farahmandi, D Forte, ...
ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (3 …, 2020
332020
Security assessment of dynamically obfuscated scan chain against oracle-guided attacks
MS Rahman, A Nahiyan, F Rahman, S Fazzari, K Plaks, F Farahmandi, ...
ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (4 …, 2021
322021
Security rule checking in IC design
K Xiao, A Nahiyan, M Tehranipoor
Computer 49 (8), 54-61, 2016
322016
Hybrid algorithm for elastography to visualize both solid and fluid-filled lesions
A Nahiyan, MK Hasan
Ultrasound in medicine & biology 41 (4), 1058-1078, 2015
252015
Standardizing bad cryptographic practice: A teardown of the IEEE standard for protecting electronic-design intellectual property
A Chhotaray, A Nahiyan, T Shrimpton, D Forte, M Tehranipoor
Proceedings of the 2017 ACM SIGSAC conference on computer and communications …, 2017
232017
Dynamically obfuscated scan chain to resist oracle-guided attacks on logic locked design
MS Rahman, A Nahiyan, S Amir, F Rahman, F Farahmandi, D Forte, ...
Cryptology ePrint Archive, 2019
182019
Code coverage analysis for IP trust verification
A Nahiyan, M Tehranipoor
Hardware IP security and trust, 53-72, 2017
142017
FLATS: filling logic and testing spatially for FPGA authentication and tamper detection
A Duncan, G Skipper, A Stern, A Nahiyan, F Rahman, A Lukefahr, ...
2019 IEEE international symposium on hardware oriented security and trust …, 2019
92019
Security rule check
A Nahiyan, K Xiao, D Forte, M Tehranipoor
Hardware IP Security and Trust, 17-36, 2017
82017
CAD framework for power side-channel vulnerability assessment
MM Tehranipoor, A Nahiyan, DJ Forte, J Park
US Patent 11,475,168, 2022
72022
Protecting obfuscated circuits against attacks that utilize test infrastructures
MM Tehranipoor, DJ Forte, F Farahmandi, A Nahiyan, F Rahman, ...
US Patent 11,222,098, 2022
72022
SeRFI: secure remote FPGA initialization in an untrusted environment
A Duncan, A Nahiyan, F Rahman, G Skipper, M Swany, A Lukefahr, ...
2020 IEEE 38th VLSI Test Symposium (VTS), 1-6, 2020
72020
Soft-HaT: Software-based silicon reprogramming for hardware Trojan implementation
MM Alam, A Nahiyan, M Sadi, D Forte, M Tehranipoor
ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (4 …, 2020
52020
RTL-PSC: automated power side-channel leakage assessment at register-transfer level
J Park, A Nahiyan, A Vassilev, Y Jin, M Tehranipoor
arXiv preprint arXiv:1901.05909, 2019
32019
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Articles 1–20