N. Nalla Anandakumar
N. Nalla Anandakumar
Senior Specialist Security Architect at Continental Automotive, Singapore
Verified email at - Homepage
Cited by
Cited by
FPGA-based true random number generation using programmable delays in oscillator-rings
NN Anandakumar, SK Sanadhya, MS Hashmi
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (3), 570-574, 2019
A very compact FPGA implementation of LED and PHOTON
N Nalla Anandakumar, T Peyrin, A Poschmann
Progress in Cryptology--INDOCRYPT 2014: 15th International Conference on …, 2014
FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures
NN Anandakumar, MS Hashmi, M Tehranipoor
Integration 81, 175-194, 2021
Compact implementations of FPGA-based PUFs with enhanced performance
NN Anandakumar, MS Hashmi, SK Sanadhya
2017 30th International Conference on VLSI Design and 2017 16th …, 2017
PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms.
J Park, NN Anandakumar, D Saha, D Mehta, N Pundir, F Rahman, ...
IACR Cryptol. ePrint Arch. 2022, 527, 2022
Efficient and lightweight FPGA-based hybrid PUFs with improved performance
NN Anandakumar, MS Hashmi, SK Sanadhya
Microprocessors and Microsystems 77, 103180, 2020
Rethinking watermark: Providing proof of IP ownership in modern socs
NN Anandakumar, MS Rahman, MMM Rahman, R Kibria, U Das, ...
Cryptology ePrint Archive, 2022
Reconfigurable hardware architecture for authenticated key agreement protocol over binary edwards curve
NN Anandakumar, MPL Das, SK Sanadhya, MS Hashmi
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (2), 1-19, 2018
SCA Resistance Analysis on FPGA Implementations of Sponge Based MAC−PHOTON
N Nalla Anandakumar
International Conference for Information Technology and Communications 9522 …, 2015
Design and Analysis of FPGA Based PUFs with Enhanced Performance for Hardware-Oriented Security
NN Anandakumar, MS Hashmi, SK Sanadhya
ACM Journal on Emerging Technologies in Computing Systems (JETC), 2022
Implementation of efficient XOR arbiter PUF on FPGA with enhanced uniqueness and security
NN Anandakumar, MS Hashmi, MA Chaudhary
IEEE Access 10, 129832-129842, 2022
Correlation power analysis attack of AES on FPGA using customized communication protocol
NN Anandakumar, S Dillibabu
Proceedings of the Second International Conference on Computational Science …, 2012
Field Programmable Gate Array based elliptic curve Menezes-Qu-Vanstone key agreement protocol realization using Physical Unclonable Function and true random number generator …
NN Anandakumar, MS Hashmi, SK Sanadhya
IET Circuits, Devices & Systems, 2022
A survey of security attacks on silicon based weak PUF architectures
C Yehoshuva, R Raja Adhithan, N Nalla Anandakumar
Security in Computing and Communications: 8th International Symposium, SSCC …, 2021
Design, implementation and analysis of efficient hardware-based security primitives
NN Anandakumar, SK Sanadhya, MS Hashmi
2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration …, 2020
Design and analysis of hardware Trojan threats in reconfigurable hardware
N Giri, NN Anandakumar
2020 International Conference on Emerging Trends in Information Technology …, 2020
FPGA Implementations of Espresso Stream Cipher
G Kumisbek, NN Anandakumar, M Hashmi
2021 28th IEEE International Conference on Electronics, Circuits, and …, 2021
Modeling attacks and efficient countermeasures on interpose PUF
R Raja Adhithan, N Nalla Anandakumar
Foundations and Practice of Security: 13th International Symposium, FPS 2020 …, 2021
Key retrieval from AES architecture through hardware Trojan horse
S Manivannan, N Nalla Anandakumar, M Nirmala Devi
Security in Computing and Communications: 6th International Symposium, SSCC …, 2019
Countermeasures Against DPA Attacks on FPGA Implementation of AES
GD Babu, NN Anandakumar, D Muralidharan
Journal of Artificial Intelligence 5 (4), 186, 2012
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