| Noxim: An open, extensible and cycle-accurate network on chip simulator V Catania, A Mineo, S Monteleone, M Palesi, D Patti 2015 IEEE 26th international conference on application-specific systems …, 2015 | 343 | 2015 |
| Multi-objective mapping for mesh-based NoC architectures G Ascia, V Catania, M Palesi Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware …, 2004 | 302 | 2004 |
| Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip G Ascia, V Catania, M Palesi, D Patti IEEE transactions on computers 57 (6), 809-820, 2008 | 287 | 2008 |
| Multi-objective design space exploration using genetic algorithms M Palesi, T Givargis Proceedings of the tenth international symposium on Hardware/software …, 2002 | 276 | 2002 |
| Cycle-accurate network on chip simulation with noxim V Catania, A Mineo, S Monteleone, M Palesi, D Patti ACM Transactions on Modeling and Computer Simulation (TOMACS) 27 (1), 1-25, 2016 | 268 | 2016 |
| Application specific routing algorithms for networks on chip M Palesi, R Holsmark, S Kumar, V Catania IEEE Transactions on Parallel and Distributed Systems 20 (3), 316-330, 2008 | 218 | 2008 |
| Noxim: Network-on-chip simulator F Fazzino, M Palesi, D Patti URL: http://sourceforge. net/projects/noxim 13, 2008 | 217 | 2008 |
| Routing algorithms in networks-on-chip M Palesi, M Daneshtalab Springer, 2014 | 135 | 2014 |
| A methodology for design of application specific deadlock-free routing algorithms for NoC systems M Palesi, R Holsmark, S Kumar, V Catania Proceedings of the 4th international conference on Hardware/software …, 2006 | 130 | 2006 |
| Efficient design space exploration for application specific systems-on-a-chip G Ascia, V Catania, AG Di Nuovo, M Palesi, D Patti Journal of Systems Architecture 53 (10), 733-750, 2007 | 127 | 2007 |
| HARAQ: congestion-aware learning model for highly adaptive routing algorithm in on-chip networks M Ebrahimi, M Daneshtalab, F Farahnakian, J Plosila, P Liljeberg, ... 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, 19-26, 2012 | 113 | 2012 |
| Data encoding schemes in networks on chip M Palesi, G Ascia, F Fazzino, V Catania IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 105 | 2011 |
| Region-based routing: a mechanism to support efficient routing algorithms in NoCs A Mejia, M Palesi, J Flich, S Kumar, P López, R Holsmark, J Duato IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (3), 356-369, 2009 | 99 | 2009 |
| Data encoding techniques for reducing energy consumption in network-on-chip N Jafarzadeh, M Palesi, A Khademzadeh, A Afzali-Kusha IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (3), 675-685, 2013 | 86 | 2013 |
| A GA-based design space exploration framework for parameterized system-on-a-chip platforms G Ascia, V Catania, M Palesi IEEE Transactions on Evolutionary Computation 8 (4), 329-346, 2004 | 83 | 2004 |
| Neighbors-on-path: A new selection strategy for on-chip networks G Ascia, V Catania, M Palesi, D Patti 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia, 79-84, 2006 | 73* | 2006 |
| An overview of efficient interconnection networks for deep neural network accelerators SM Nabavinejad, M Baharloo, KC Chen, M Palesi, T Kogel, M Ebrahimi IEEE Journal on Emerging and Selected Topics in Circuits and Systems 10 (3 …, 2020 | 70 | 2020 |
| A method for router table compression for application specific routing in mesh topology NoC architectures M Palesi, S Kumar, R Holsmark Embedded Computer Systems: Architectures, Modeling, and Simulation: 6th …, 2006 | 66 | 2006 |
| ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform A Monemi, JW Tang, M Palesi, MN Marsono Microprocessors and Microsystems 54, 60-74, 2017 | 65 | 2017 |
| A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. G Ascia, V Catania, M Palesi J. Univers. Comput. Sci. 12 (4), 370-394, 2006 | 63 | 2006 |
Davide PattiUniversity of CataniaVerified email at dieei.unict.it
