| An area and power efficient design of single edge triggered D-flip flop M Sharma, A Noor, SC Tiwari, K Singh 2009 International Conference on Advances in Recent Technologies in …, 2009 | 35 | 2009 |
| Robust stego-key directed LSB substitution scheme based upon cuckoo search and chaotic map GS Walia, S Makhija, K Singh, K Sharma Optik 170, 106-124, 2018 | 22 | 2018 |
| Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms K Singh, A Jain, A Mittal, V Yadav, AA Singh, AK Jain, M Gupta Integration 60, 25-38, 2018 | 18 | 2018 |
| Design and analysis of adaptive graph based cancelable multi-biometrics approach GS Walia, K Aggarwal, K Singh, K Singh IEEE Transactions on Dependable and Secure Computing, 2020 | 17 | 2020 |
| A modified implementation of tristate inverter based static master-slave flip-flop with improved power-delay-area product K Singh, SC Tiwari, M Gupta The Scientific World Journal 2014, 2014 | 15 | 2014 |
| Design and Investigation of Split-Gate MoTe2-Based FET as Single Transistor AND Gate Using Nonequilibrium Green’s Function P Kumar, M Gupta, K Singh, N Kumar IEEE Transactions on Electron Devices 67 (11), 5221-5228, 2020 | 13 | 2020 |
| Performance evaluation of transition metal Dichalcogenides based steep subthreshold slope tunnel field effect transistor P Kumar, M Gupta, K Singh Silicon, 1-8, 2019 | 11 | 2019 |
| A high performance flip flop for low power low voltage systems K Singh, SC Tiwari, M Gupta 2011 World Congress on Information and Communication Technologies, 257-262, 2011 | 6 | 2011 |
| A low power high density double edge triggered flip flop for low voltage systems SC Tiwari, K Singh, M Gupta 2010 International Conference on Advances in Recent Technologies in …, 2010 | 6 | 2010 |
| Performance analysis of charge plasma based five layered black phosphorus-silicon heterostructure tunnel field effect transistor P Kumar, M Gupta, K Singh Silicon, 1-9, 2020 | 5 | 2020 |
| Implementation of High Performance Clock-gated Flip-flops P Kumar, K Singh 2018 2nd IEEE International Conference on Power Electronics, Intelligent …, 2018 | 4 | 2018 |
| A closed-loop ASIC design approach based on logical effort theory and artificial neural networks K Singh, SC Tiwari, M Gupta Integration 69, 10-22, 2019 | 2 | 2019 |
| Standard test bench for optimization and characterization of combinational circuits SC Tiwari, MA Khan, K Singh, A Sangal 2012 IEEE International Conference on Signal Processing, Computing and …, 2012 | 2 | 2012 |
| Back-Gated MoTe 2 Based 1T-AND Gate Using Non-equilibrium Green’s Function: Design and Investigation P Kumar, M Gupta, K Singh, N Kumar Journal of Electronic Materials, 1-7, 2021 | 1 | 2021 |
| Analysis of Transition Metal Dichalcogenide Materials Based Nanotube P Kumar, M Gupta, K Singh Advances in Electromechanical Technologies, 681-689, 2021 | 1 | 2021 |
| Interior Search Algorithm integrated Matlab-SPICE Interface for Optimization of CMOS Inverter Switching Characteristics V Saxena, N Sreejeth, K Singh 2020 IEEE International Conference for Innovation in Technology (INOCON), 1-6, 2020 | 1 | 2020 |
| Low Leakage Current Molybdenum Ditelluride based nano FET using Non-Equilbrium Greens Function P Kumar, M Gupta, K Singh 2020 7th International Conference on Signal Processing and Integrated …, 2020 | 1 | 2020 |
| Logical effort based automated transistor width optimization methodology SC Tiwari, A Gupta, K Singh, M Gupta 2011 World Congress on Information and Communication Technologies, 1067-1072, 2011 | 1 | 2011 |
| A novel methodology for flip-flop optimization and characterization in NOC design space SC Tiwari, K Singh, M Gupta 2011 World Congress on Information and Communication Technologies, 251-256, 2011 | 1 | 2011 |
| Performance Optimization of Digital CMOS Integrated Circuits using LE Theory and APSO R Kukreti, K Singh 2019 International Conference on Computing, Power and Communication …, 2019 | | 2019 |
