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Parag Upadhyaya
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A 56-Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16-nm FinFET
Y Frans, J Shin, L Zhou, P Upadhyaya, J Im, V Kireev, M Elzeftawi, ...
IEEE journal of solid-state circuits 52 (4), 1101-1110, 2017
1862017
A 40-to-56 Gb/s PAM-4 receiver with ten-tap direct decision-feedback equalization in 16-nm FinFET
J Im, D Freitas, AB Roldan, R Casey, S Chen, CHA Chou, T Cronin, ...
IEEE Journal of Solid-State Circuits 52 (12), 3486-3502, 2017
1192017
A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET
P Upadhyaya, CF Poon, SW Lim, J Cho, A Roldan, W Zhang, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 108-110, 2018
822018
A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs
D Turker, A Bekele, P Upadhyaya, B Verbruggen, Y Cao, S Ma, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 378-380, 2018
742018
2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS
JC Chien, P Upadhyaya, H Jung, S Chen, W Fang, AM Niknejad, J Savoj, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
692014
3.3 A 0.5-to-32.75 Gb/s flexible-reach wireline transceiver in 20nm CMOS
P Upadhyaya, J Savoj, FT An, A Bekele, A Jose, B Xu, D Wu, D Turker, ...
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
502015
A 40-to-64 Gb/s NRZ transmitter with supply-regulated front-end in 16 nm FinFET
Y Frans, S McLeod, H Hedayati, M Elzeftawi, J Namkoong, W Lin, J Im, ...
IEEE Journal of Solid-State Circuits 51 (12), 3167-3177, 2016
442016
A novel SiGe PIN diode SPST switch for broadband T/R module
P Sun, P Upadhyaya, DH Jeong, D Heo, GS La Rue
IEEE microwave and wireless components letters 17 (5), 352-354, 2007
442007
A 32.75-Gb/s voltage-mode transmitter with three-tap FFE in 16-nm CMOS
KL Chan, KH Tan, Y Frans, J Im, P Upadhyaya, SW Lim, A Roldan, ...
IEEE Journal of Solid-State Circuits 52 (10), 2663-2678, 2017
422017
Design of high-speed wireline transceivers for backplane communications in 28nm CMOS
J Savoj, K Hsieh, P Upadhyaya, FT An, J Im, X Jiang, J Kamali, KW Lai, ...
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012
382012
A 112GB/S PAM4 wireline receiver using a 64-way time-interleaved SAR ADC in 16NM FinFET
J Hudner, D Carey, R Casey, K Hearne, PWAF Neto, I Chlis, M Erett, ...
2018 IEEE Symposium on VLSI Circuits, 47-48, 2018
362018
A wide common-mode fully-adaptive multi-standard 12.5 gb/s backplane transceiver in 28nm cmos
J Savoj, K Hsieh, P Upadhyaya, FT An, A Bekele, S Chen, X Jiang, ...
2012 Symposium on VLSI Circuits (VLSIC), 104-105, 2012
362012
A fully adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ wireline transceiver with configurable ADC in 16-nm FinFET
P Upadhyaya, CF Poon, SW Lim, J Cho, A Roldan, W Zhang, ...
IEEE Journal of Solid-State Circuits 54 (1), 18-28, 2018
342018
A 0.5–16.3 Gb/s fully adaptive flexible-reach transceiver for FPGA in 20 nm CMOS
Y Frans, D Carey, M Erett, H Amir-Aslanzadeh, WY Fang, D Turker, ...
IEEE Journal of Solid-State Circuits 50 (8), 1932-1944, 2015
342015
A compact 5.6 GHz low noise amplifier with new on-chip gain controllable active balun
M Rajashekharaiah, P Upadhyaya, D Heo
2004 IEEE Workshop on Microelectronics and Electron Devices, 131-132, 2004
342004
A 5.6-GHz CMOS doubly balanced sub-harmonic mixer for direct conversion-zero IF receiver
P Upadhyaya, M Rajashekharaiah, D Heo
2004 IEEE Workshop on Microelectronics and Electron Devices, 129-130, 2004
342004
A 112-Gb/s PAM4 transmitter in 16nm FinFET
KH Tan, PC Chiang, Y Wang, H Zhao, A Roldan, H Zhao, N Narang, ...
2018 IEEE Symposium on VLSI Circuits, 45-46, 2018
322018
A new gain controllable on-chip active balun for 5 GHz direct conversion receiver
M Rajashekharaiah, P Upadhyaya, D Heo, E Chen
2005 IEEE International Symposium on Circuits and Systems (ISCAS), 5115-5118, 2005
302005
A 164fsrms 9-to-18GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16nm FinFET
M Raj, A Bekele, D Turker, P Upadhyaya, Y Frans, K Chang
2017 Symposium on VLSI Circuits, C182-C183, 2017
282017
Injection-controlled-locked phase-locked loop
JC Chien, W Fang, P Upadhyaya, J Savoj, KY Chang
US Patent 8,841,948, 2014
252014
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