| Quantum dot cellular automata based effective design of combinational and sequential logical structures HS Jagarlamudi, M Saha, PK Jagarlamudi World Academy of Science, Engineering and Technology 60, 671-675, 2011 | 36 | 2011 |
| Synthesis of reversible universal logic around QCA with online testability B Sen, D Saran, M Saha, BK Sikdar 2011 International Symposium on Electronic System Design, 236-241, 2011 | 31 | 2011 |
| On automatizing recognition of multiple human activities using ultrasonic sensor grid A Ghosh, A Sanyal, A Chakraborty, PK Sharma, M Saha, S Nandi, S Saha 2017 9th international conference on communication systems and networks …, 2017 | 29 | 2017 |
| Can we recognize multiple human group activities using ultrasonic sensors? A Ghosh, D Chakraborty, D Prasad, M Saha, S Saha 2018 10th International Conference on Communication Systems & Networks …, 2018 | 12 | 2018 |
| On detecting acceptable air contamination in classrooms using low cost sensors PK Sharma, B Poddar, S Dey, S Nandi, T De, M Saha, S Mondal, S Saha 2017 9th international conference on communication systems and networks …, 2017 | 10 | 2017 |
| A cellular automata based highly accurate memory test hardware realizing March C− M Saha, M Dalui, BK Sikdar Microelectronics journal 52, 91-103, 2016 | 9 | 2016 |
| High Speed Hardware for March C¯ M Saha, S Das, BK Sikdar 2012 International Symposium on Electronic System Design (ISED), 145-147, 2012 | 8 | 2012 |
| An efficient auction based TATKAL scheme for Indian Railway S Mukhopadhyay, N Mukherjee, J Bhattacharjee, D Ghosh, M Saha, ... 2010 International Conference on Innovative Computing and Communication and …, 2010 | 8 | 2010 |
| Cellular automata based fault tolerant resistive memory design M Saha, S Sarkar, BK Sikdar 2016 Sixth International Symposium on Embedded Computing and System Design …, 2016 | 7 | 2016 |
| Multi-bit fault tolerant design for resistive memories through dynamic partitioning S Sarkar, M Saha, BK Sikdar 2017 IEEE East-West Design & Test Symposium (EWDTS), 1-6, 2017 | 6 | 2017 |
| Periodic boundary cellular automata based test structure for memory M Saha, B Das, BK Sikdar 2017 IEEE East-West Design & Test Symposium (EWDTS), 1-6, 2017 | 6 | 2017 |
| An efficient method for testing of L1 cache module in tiled CMPs architecture at low cost M Saha, BK Sikdar 2015 International Conference on VLSI Systems, Architecture, Technology and …, 2015 | 5 | 2015 |
| A cellular automata based design of self testable hardware for March C− M Saha, BK Sikdar 2013 International Conference on High Performance Computing & Simulation …, 2013 | 5 | 2013 |
| Poster: Air quality monitoring using low-cost sensingdevices A Ghosh, S Mondal, M Saha, S Saha, S Nandi Proceedings of the 14th Annual International Conference on Mobile Systems …, 2016 | 4 | 2016 |
| A self testable hardware for memory M Saha, BK Sikdar 2013 IEEE International Conference on Circuits and Systems (ICCAS), 45-50, 2013 | 4 | 2013 |
| A cellular automata based high speed test hardware for word-organized memories M Saha, BK Sikdar 2012 International Conference on Devices, Circuits and Systems (ICDCS), 345-349, 2012 | 4 | 2012 |
| BIST Design For Static Neighbourhood Pattern Sensitive Fault Test A Samanta, M Saha, AK Mahato Int. J. Comput. Appl, 0975-8887, 0 | 3 | |
| Exploring visible light communication system using rts/cts mechanism for mobile environment KN Datta, P Das, M Saha, S Saha, S Chakraborty Proceedings of the 24th Annual International Conference on Mobile Computing …, 2018 | 1 | 2018 |
| Test structure for L1 cache in tiled CMPs M Saha, BK Sikder IAENG Int J Comput Sci 43 (3), 392-401, 2016 | 1 | 2016 |
| A cellular automata based fault tolerant approach in designing test hardware for L1 cache module M Saha, BK Sikdar 2015 IEEE Computer Society Annual Symposium on VLSI, 497-502, 2015 | 1 | 2015 |
Biplab Kumar SikdarIndian Institute of Engineering Science and TechnologyVerified email at cs.iiests.ac.in
