Representative critical reliability paths for low-cost and accurate on-chip aging evaluation S Wang, J Chen, M Tehranipoor Proceedings of the International Conference on Computer-Aided Design, 736-741, 2012 | 65 | 2012 |
Efficient selection and analysis of critical-reliability paths and gates J Chen, S Wang, M Tehranipoor Proceedings of the great lakes symposium on VLSI, 45-50, 2012 | 40 | 2012 |
Thread-associative memory for multicore and multithreaded computing S Wang, L Wang Proceedings of the 2006 international symposium on Low power electronics and …, 2006 | 21 | 2006 |
Critical-reliability path identification and delay analysis J Chen, S Wang, M Tehranipoor ACM Journal on Emerging Technologies in Computing Systems (JETC) 10 (2), 12, 2014 | 15 | 2014 |
In-field aging measurement and calibration for power-performance optimization S Wang, M Tehranipoor, LR Winemberg Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, 706-711, 2011 | 15 | 2011 |
A framework for fast and accurate critical-reliability paths identification J Chen, S Wang, N Bidokhti, M Tehranipoor Proceedings of the IEEE North Atlantic Test Workshop (NATW), 2011 | 12 | 2011 |
Programmable threshold voltage using quantum dot transistors for low-power mobile computing S Wang, J Dai, ES Hasaneen, L Wang, F Jain 2008 IEEE International Symposium on Circuits and Systems, 3350-3353, 2008 | 8 | 2008 |
Dynamic redundancy allocation for reliable and high-performance nanocomputing S Wang, L Wang, F Jain 2007 IEEE International Symposium on Nanoscale Architectures, 1-6, 2007 | 7 | 2007 |
Light-weight on-chip structure for measuring timing uncertainty induced by noise in integrated circuits S Wang, M Tehranipoor IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (5 …, 2014 | 6 | 2014 |
Making register file resistant to power analysis attacks S Wang, F Zhang, J Dai, L Wang, ZJ Shi Computer Design, 2008. ICCD 2008. IEEE International Conference on, 577-582, 2008 | 6 | 2008 |
Exploiting memory soft redundancy for joint improvement of error tolerance and access efficiency S Wang, L Wang IEEE transactions on very large scale integration (VLSI) systems 17 (8), 973-982, 2009 | 5 | 2009 |
Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation S Wang, L Wang, F Jain ACM Journal on Emerging Technologies in Computing Systems (JETC) 5 (1), 2, 2009 | 5 | 2009 |
Exploiting soft redundancy for error-resilient on-chip memory design S Wang, L Wang Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 5 | 2006 |
Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency................... S Wang, L Wang | 5* | |
TSUNAMI: a light-weight on-chip structure for measuring timing uncertainty induced by noise during functional and test operations S Wang, M Tehranipoor Proceedings of the great lakes symposium on VLSI, 183-188, 2012 | 4 | 2012 |
Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing S Wang, J Dai, ES Hasaneen, L Wang, F Jain ACM Journal on Emerging Technologies in Computing Systems (JETC) 5 (3), 15, 2009 | 4 | 2009 |
Analysis of deskew signaling via adaptive timing S Wang, L Wang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 4 | 2009 |
A defect-tolerant memory nanoarchitecture exploiting hybrid redundancy S Wang, L Wang 2008 8th IEEE Conference on Nanotechnology, 707-710, 2008 | 4 | 2008 |
Experimental analysis for aging in integrated circuits N Reddy, S Wang, L Winemberg, M Tehranipoor IEEE North Atlantic Test Workshop (NATW), 2011 | 3 | 2011 |
Design of error-tolerant cache memory for multithreaded computing S Wang, L Wang 2008 IEEE International Symposium on Circuits and Systems, 1890-1893, 2008 | 3 | 2008 |