James Tuck

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Josep TorrellasProfessor of Computer Science, University of Illinois Urbana-ChampaignVerified email at illinois.edu
Luis CezeProfessor of Computer Science and Engineering, University of WashingtonVerified email at cs.washington.edu
Jose RenauProcessor of Computer Science Engineering, UCSCVerified email at ucsc.edu
Karin StraussMicrosoft ResearchVerified email at microsoft.com
Pablo MontesinosAppleVerified email at apple.com
Wonsun AhnUniversity of PittsburghVerified email at cs.pitt.edu
Albert J KeungNorth Carolina State UniversityVerified email at ncsu.edu
Smruti R. SarangiComputer Science, IIT DelhiVerified email at cse.iitd.ac.in
Milos PrvulovicProfessor of Computer Science, Georgia TechVerified email at cc.gatech.edu
Calin CascavalGoogleVerified email at cascaval.us
Mohammad A. AlshboulJordan University of Science and TechnologyVerified email at just.edu.jo
Basilio B. FraguelaUniversidade da Coruña, Centro de investigación CITIC, Depto. de Enxeñaría de ComputadoresVerified email at udc.es
Eric RotenbergNorth Carolina State UniversityVerified email at ncsu.edu
Ted BaptyVanderbilt UniversityVerified email at isis.vanderbilt.edu
Rajeshwar VankaGoogleVerified email at google.com
Hussein ElnawawyGoogle, Inc.Verified email at google.com
Jeff GrayProfessor, Department of Computer Science; Director, Randall Research Scholars - U. AlabamaVerified email at cs.ua.edu
Sandeep NeemaResearch Professor, Vanderbilt UniversityVerified email at vanderbilt.edu
Terri A. LongPlant Biology, North Carolina State UniversityVerified email at ncsu.edu
Alexandr KoryachkoPhD student in Electrical Engineering, NCSUVerified email at ncsu.edu

James Tuck

Professor of Electrical and Computer Engineering at North Carolina State University

Verified email at ncsu.edu - Homepage

DNA Storage Computer Architecture Compilers Computer Systems


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Bulk disambiguation of speculative threads in multiprocessors L Ceze, J Tuck, J Torrellas, C Cascaval ACM SIGARCH Computer Architecture News 34 (2), 227-238, 2006	423	2006
SESC simulator, January 2005 J Renau, B Fraguela, J Tuck, W Liu, M Prvulovic, L Ceze, S Sarangi, ...	340	2005
POSH: a TLS compiler that exploits program structure W Liu, J Tuck, L Ceze, W Ahn, K Strauss, J Renau, J Torrellas Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice …, 2006	330	2006
BulkSC: Bulk enforcement of sequential consistency L Ceze, J Tuck, P Montesinos, J Torrellas Proceedings of the 34th annual international symposium on Computer …, 2007	316	2007
Handling crosscutting constraints in domain-specific modeling J Gray, T Bapty, S Neema, J Tuck Communications of the ACM 44 (10), 87-93, 2001	216	2001
Tasking with out-of-order spawn in TLS chip multiprocessors: Microarchitecture and compilation J Renau, J Tuck, W Liu, L Ceze, K Strauss, J Torrellas Proceedings of the 19th Annual International conference on Supercomputing …, 2005	126	2005
Proteus: A flexible and fast software supported hardware logging approach for nvm S Shin, SK Tirukkovalluri, J Tuck, Y Solihin Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017	124	2017
Scalable cache miss handling for high memory-level parallelism J Tuck, L Ceze, J Torrellas 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006	105	2006
DNA stability: a central design consideration for DNA data storage systems K Matange, JM Tuck, AJ Keung Nature communications 12 (1), 1-9, 2021	101	2021
Driving the scalability of DNA-based information storage systems KJ Tomek, K Volkel, A Simpson, AG Hass, EW Indermaur, JM Tuck, ... ACS synthetic biology 8 (6), 1241-1248, 2019	74	2019
Hiding the long latency of persist barriers using speculative execution S Shin, J Tuck, Y Solihin Proceedings of the 44th Annual International Symposium on Computer …, 2017	71	2017
Dynamic and scalable DNA-based information storage KN Lin, K Volkel, JM Tuck, AJ Keung Nature communications 11 (1), 2981, 2020	66	2020
Thread-level speculation on a CMP can be energy efficient J Renau, K Strauss, L Ceze, W Liu, S Sarangi, J Tuck, J Torrellas Proceedings of the 19th annual international conference on Supercomputing …, 2005	58	2005
CAVA: Using checkpoint-assisted value prediction to hide L2 misses L Ceze, K Strauss, J Tuck, J Torrellas, J Renau ACM Transactions on Architecture and Code Optimization (TACO) 3 (2), 182-208, 2006	55	2006
Lazy persistency: A high-performing and write-efficient software persistency technique M Alshboul, J Tuck, Y Solihin 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018	50	2018
System and method for non-uniform cache in a multi-core processor C Hughes, J Tuck, V Lee, YK Chen US Patent App. 11/023,925, 2006	50	2006
SoftSig: software-exposed hardware signatures for code analysis and optimization J Tuck, W Ahn, L Ceze, J Torrellas ACM SIGOPS Operating Systems Review 42 (2), 145-156, 2008	49	2008
Efficient checkpointing of loop-based codes for non-volatile main memory H Elnawawy, M Alshboul, J Tuck, Y Solihin 2017 26th International Conference on Parallel Architectures and Compilation …, 2017	47	2017
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor S Lee, D Tiwari, Y Solihin, J Tuck 2011 IEEE 17th International Symposium on High Performance Computer …, 2011	45	2011
Energy-efficient thread-level speculation J Renau, K Strauss, L Ceze, W Liu, SR Sarangi, J Tuck, J Torrellas IEEE Micro 26 (1), 80-91, 2006	38	2006

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