Hao Li
Hao Li
Marvell Semiconductor Inc.
Verificeret mail på brown.edu
Citeret af
Citeret af
Wireless neurosensor for full-spectrum electrophysiology recordings during free behavior
M Yin, DA Borton, J Komar, N Agha, Y Lu, H Li, J Laurens, Y Lang, Q Li, ...
Neuron 84 (6), 1170-1182, 2014
A fully fledged TDC implemented in field-programmable gate arrays
J Wang, S Liu, Q Shen, H Li, Q An
IEEE Transactions on Nuclear Science 57 (2), 446-450, 2010
A fast digital predistortion algorithm for radio-frequency power amplifier linearization with loop delay compensation
H Li, DH Kwon, D Chen, Y Chiu
IEEE Journal of selected topics in signal processing 3 (3), 374-383, 2009
9.4 A 2× 2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation
R Winoto, A Olyaei, M Hajirostam, W Lau, X Gao, A Mitra, O Carnu, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 170-171, 2016
A four-channel beamforming down-converter in 90-nm CMOS utilizing phase-oversampling
R Tseng, H Li, DH Kwon, Y Chiu, ASY Poon
IEEE journal of solid-state circuits 45 (11), 2262-2272, 2010
A virtual-ADC digital background calibration technique for multistage A/D conversion
B Peng, H Li, SC Lee, P Lin, Y Chiu
IEEE Transactions on Circuits and Systems II: Express Briefs 57 (11), 853-857, 2010
An offset double conversion technique for digital calibration of pipelined ADCs
B Peng, H Li, P Lin, Y Chiu
IEEE Transactions on Circuits and Systems II: Express Briefs 57 (12), 961-965, 2010
A 48-mW, 12-bit, 150MS/s pipelined ADC with digital calibration in 65nm CMOS
PL B Peng, G. Huang, H. Li, P. Wan
IEEE Custom Integrated Circuits Conference, 2011
An externally head-mounted wireless neural recording device for laboratory animal research and possible human clinical use
M Yin, H Li, C Bull, DA Borton, J Aceros, L Larson, AV Nurmikko
2013 35th Annual International Conference of the IEEE Engineering in …, 2013
Digitally equalized CMOS transmitter front-end with integrated power amplifier
DH Kwon, H Li, Y Chang, R Tseng, Y Chiu
IEEE journal of solid-state circuits 45 (8), 1602-1614, 2010
13.7 A 0.23mm2 digital power amplifier with hybrid time/amplitude control achieving 22.5dBm at 28% PAE for 802.11g
D Cousinard, R Winoto, H Li, Y Fang, A Ghaffari, A Olyaei, O Carnu, ...
2017 IEEE International Solid-State Circuits Conference (ISSCC), 228-229, 2017
TOF clock system for BES III
H Li, S Liu, C Feng, S Tang, Q An
2009 16th IEEE-NPSS Real Time Conference, 522-526, 2009
A dual core power combining digital power amplifier for 802.11 b/g/n with+ 26.8 dBm linear output power in 28nm CMOS
A Wong, P Godoy, O Carnu, H Li, X Zhao, A Olyaei, A Ghaffari, SW Tam, ...
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 192-195, 2017
BESⅢ 飞行时间计数器前端电子学测试系统设计
郭建华, 刘树彬, 封常青, 李浩, 安琪
核技术 30 (7), 610-614, 2007
An inherently linear phase-oversampling vector modulator in 90-nm CMOS
R Tseng, H Li, DH Kwon, ASY Poon, Y Chiu
2009 IEEE Asian Solid-State Circuits Conference, 257-260, 2009
CMOS RF transmitter with integrated power amplifier utilizing digital equalization
DH Kwon, H Li, Y Chang, R Tseng, Y Chiu
2009 IEEE Custom Integrated Circuits Conference, 403-406, 2009
Adaptive digital techniques for efficiency and linearity enhancement of CMOS RF power amplifiers
DH Kwon, H Li, Y Chiu
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI …, 2008
A BiCMOS 50 MHz input bandwidth, 1-to-16 channelizer optimized for low power analog signal classification
H Li, CM Thomas, G Cauwenberghs, LE Larson
2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 76-79, 2014
A modified background calibration technique for multi-bit delta-sigma modulators
B Peng, H Li, P Lin
2011 3rd International Conference on Advanced Computer Control, 206-208, 2011
基于 VME 总线的多通道定标器
李浩, 刘树彬, 安琪
核电子学与探测技术, 2008
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Artikler 1–20