| Improvement of timing specifications in second order electronic systems using programmable CMOS Posicast pulse shapers M Rahimi, MB Ghaznavi-Ghoushchi 20th Iranian Conference on Electrical Engineering (ICEE2012), 309-313, 2012 | 5 | 2012 |
| A low-power and high-speed parallel binary comparator based on inter-stage modified binary tree structure and power-delay improved cell elements M Rahimi, MB Ghaznavi-Ghoushchi Microelectronics Journal 88, 37-46, 2019 | 4 | 2019 |
| A 98.1 % CE, 100 mA MLC multi-reference output all digital LDO with fast settling and digital self calibration for DVFS and multi-VDD applications S Kaedi, MB Ghaznavi-Ghoushchi, M Rahimi Analog Integrated Circuits and Signal Processing 89 (2), 437-450, 2016 | 4 | 2016 |
| A power efficient multi-level output all digital LDO with fast settling time and built in self calibration for DVFS and multi-VDD applications S Kaedi, MB Ghaznavi-Ghoushchi, M Rahimi 2015 23rd Iranian Conference on Electrical Engineering, 1276-1281, 2015 | 3 | 2015 |
| A novel generic modulo-2 graph with full set taxonomical conversion to parallel prefix adders M Rahimi, MB Ghaznavi-Ghoushchi International Journal of Circuit Theory and Applications 2022 (Early Access …, 2022 | 2 | 2022 |
| A fanout-improved Parallel Prefix Adder with full-swing PTL cells and Graded Bit Efficiency M Rahimi, MB Ghaznavi-Ghoushchi Microelectronics Journal 113, 105086, 2021 | 1 | 2021 |
| A Silicon Neuron-based Bio-Front-End for Ultra Low Power Bio-Monitoring at the Edge TP Shivangi, M Rahimi, G Gargiulo, BJ Kailath, TJ Hamilton 2020 IEEE Symposium Series on Computational Intelligence (SSCI), 3043-3048, 2020 | | 2020 |
| Design and Implementation of an Improved Programmable Circuit for Overshoot Reduction by PosicastTechnique M Rahimi, MB Ghaznavi-Ghoushchi صنايع الکترونيک, 2013 | | 2013 |
