Li Jiang
Cited by
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Perceived colleagues’ safety knowledge/behavior and safety performance: Safety climate as a moderator in a multilevel study
L Jiang, G Yu, Y Li, F Li
Accident analysis & prevention 42 (5), 1468-1476, 2010
Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar
L Chen, J Li, Y Chen, Q Deng, J Shen, X Liang, L Jiang
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 19-24, 2017
Test architecture design and optimization for three-dimensional SoCs
L Jiang, L Huang, Q Xu
2009 Design, Automation & Test in Europe Conference & Exhibition, 220-225, 2009
On effective TSV repair for 3D-stacked ICs
L Jiang, Q Xu, B Eklow
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 793-798, 2012
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
L Jiang, Q Xu, K Chakrabarty, TM Mak
Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009
Drq: dynamic region-based quantization for deep neural network acceleration
Z Song, B Fu, F Wu, Z Jiang, L Jiang, N Jing, X Liang
2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020
On effective through-silicon via repair for 3-D-stacked ICs
L Jiang, Q Xu, B Eklow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
Yield enhancement for 3D-stacked memory by redundancy sharing across dies
L Jiang, R Ye, Q Xu
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 230-234, 2010
ReCom: An efficient resistive accelerator for compressed deep neural networks
H Ji, L Song, L Jiang, H Li, Y Chen
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 237-240, 2018
System-level hardware failure prediction using deep learning
X Sun, K Chakrabarty, R Huang, Y Chen, B Zhao, H Cao, Y Han, X Liang, ...
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
Automated rule-based constructability checking: Case study of formwork
L Jiang, RM Leicht
Journal of Management in Engineering 31 (1), A4014004, 2015
PIM-prune: Fine-grain DCNN pruning for crossbar-based process-in-memory architecture
C Chu, Y Wang, Y Zhao, X Ma, S Ye, Y Hong, X Liang, Y Han, L Jiang
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
An ultra-efficient memristor-based DNN framework with structured weight pruning and quantization using ADMM
G Yuan, X Ma, C Ding, S Lin, T Zhang, ZS Jalali, Y Zhao, L Jiang, ...
2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019
On effective and efficient in-field TSV repair for stacked 3D ICs
L Jiang, F Ye, Q Xu, K Chakrabarty, B Eklow
Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013
SSTDP: Supervised spike timing dependent plasticity for efficient spiking neural network training
F Liu, W Zhao, Y Chen, Z Wang, T Yang, L Jiang
Frontiers in Neuroscience 15, 756876, 2021
Improving neural network efficiency via post-training quantization with adaptive floating-point
F Liu, W Zhao, Z He, Y Wang, Z Wang, C Dai, X Liang, L Jiang
Proceedings of the IEEE/CVF international conference on computer vision …, 2021
Yield enhancement for 3D-stacked ICs: Recent advances and challenges
Q Xu, L Jiang, H Li, B Eklow
17th Asia and South Pacific Design Automation Conference, 731-737, 2012
Modeling TSV open defects in 3D-stacked DRAM
L Jiang, Y Liu, L Duan, Y Xie, Q Xu
2010 IEEE International Test Conference, 1-9, 2010
Spikeconverter: An efficient conversion framework zipping the gap between artificial neural networks and spiking neural networks
F Liu, W Zhao, Y Chen, Z Wang, L Jiang
Proceedings of the AAAI Conference on Artificial Intelligence 36 (2), 1692-1701, 2022
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs
N Jing, J Wang, F Fan, W Yu, L Jiang, C Li, X Liang
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
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