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Ashish Ranjan
Ashish Ranjan
Research Staff Member, IBM T.J. Watson Research Center
Verified email at ibm.com - Homepage
Title
Cited by
Cited by
Year
Computing in memory with spin-transfer torque magnetic ram
S Jain, A Ranjan, K Roy, A Raghunathan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (3), 470-483, 2017
3432017
AxNN: Energy-efficient neuromorphic systems using approximate computing
S Venkataramani, A Ranjan, K Roy, A Raghunathan
Proceedings of the 2014 international symposium on Low power electronics and …, 2014
3202014
Scaledeep: A scalable compute architecture for learning and evaluating deep networks
S Venkataramani, A Ranjan, S Banerjee, D Das, S Avancha, ...
Proceedings of the 44th Annual International Symposium on Computer …, 2017
2632017
ASLAN: Synthesis of approximate sequential circuits
A Ranjan, A Raha, S Venkataramani, K Roy, A Raghunathan
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
1612014
Approximate storage for energy efficient spintronic memories
A Ranjan, S Venkataramani, X Fong, K Roy, A Raghunathan
Proceedings of the 52nd Annual Design Automation Conference, 195, 2015
1142015
RaPiD: AI Accelerator for Ultra-low Precision Training and Inference
S Venkataramani, V Srinivasan, W Wang, S Sen, J Zhang, A Agrawal, ...
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021
642021
Apparatuses, methods, and systems for neural networks
S Venkataramani, D Das, A Ranjan, S Banerjee, S Avancha, ...
US Patent App. 16/317,497, 2019
522019
STAxCache: An approximate, energy efficient STT-MRAM cache
A Ranjan, S Venkataramani, Z Pajouhi, R Venkatesan, K Roy, ...
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
502017
X-MANN: A crossbar based architecture for memory augmented neural networks
A Ranjan, S Jain, JR Stevens, D Das, B Kaul, A Raghunathan
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
402019
Approximate memory compression for energy-efficiency
A Ranjan, A Raha, V Raghunathan, A Raghunathan
2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017
362017
AxBA: An approximate bus architecture framework
JR Stevens, A Ranjan, A Raghunathan
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018
302018
System and method for in-memory computing
S Jain, A Ranjan, K Roy, A Raghunathan
US Patent 10,073,733, 2018
262018
Approximate Memory Compression
A Ranjan, A Raha, V Raghunathan, A Raghunathan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (4), 980-991, 2020
252020
Manna: An Accelerator for Memory-Augmented Neural Networks
JR Stevens, A Ranjan, D Das, B Kaul, A Raghunathan
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
252019
Dyrectape: a dynamically reconfigurable cache using domain wall memory tapes
A Ranjan, SG Ramasubramanian, R Venkatesan, V Pai, K Roy, ...
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 181-186, 2015
202015
System and method for in-memory computing
S Jain, A Ranjan, K Roy, A Raghunathan
US Patent App. 10/073,733, 2018
14*2018
Cache Memory Design With Magnetic Skyrmions in a Long Nanotrack
MC Chen, A Ranjan, A Raghunathan, K Roy
IEEE Transactions on Magnetics 55 (8), 1-9, 2019
82019
Emerging neural workloads and their impact on hardware
D Brooks, MM Frank, T Gokmen, U Gupta, XS Hu, S Jain, AF Laguna, ...
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020
52020
Apparatuses, methods, and systems for access synchronization in a shared memory
S Venkataramani, D Das, S Avancha, A Ranjan, S Banerjee, K Bharat, ...
US Patent 11,106,464, 2021
42021
Memory controller that forces prefetches in response to a present row address change timing constraint
A Ranjan, V Kozhikkottu
US Patent 10,268,585, 2019
42019
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