| Low-latency virtual-channel routers for on-chip networks R Mullins, A West, S Moore ACM SIGARCH Computer Architecture News 32 (2), 188, 2004 | 661 | 2004 |
| Dynamic channel pruning: Feature boosting and suppression X Gao, Y Zhao, Ł Dudziak, R Mullins, C Xu ICLR 2019, 2019 | 284 | 2019 |
| Improving smart card security using self-timed circuits S Moore, R Anderson, P Cunningham, R Mullins, G Taylor Proceedings Eighth International Symposium on Asynchronous Circuits and …, 2002 | 279 | 2002 |
| Point to point GALS interconnect S Moore, G Taylor, R Mullins, P Robinson Asynchronous Circuits and Systems, 2002. Proceedings. Eighth International …, 2002 | 187 | 2002 |
| The design and implementation of a low-latency on-chip network R Mullins, A West, S Moore Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 175 | 2006 |
| A power and energy exploration of network-on-chip architectures A Banerjee, R Mullins, S Moore First International Symposium on Networks-on-Chip (NOCS'07), 163-172, 2007 | 146 | 2007 |
| Balanced self-checking asynchronous logic for smart card applications S Moore, R Anderson, R Mullins, G Taylor, JJA Fournier Microprocessors and Microsystems 27 (9), 421-430, 2003 | 138 | 2003 |
| Security evaluation of asynchronous circuits JJA Fournier, S Moore, H Li, R Mullins, G Taylor Cryptographic Hardware and Embedded Systems-CHES 2003: 5th International …, 2003 | 129 | 2003 |
| Commodity single board computer clusters and their applications SJ Johnston, PJ Basford, CS Perkins, H Herry, FP Tso, D Pezaros, ... Future Generation Computer Systems, 2018 | 100 | 2018 |
| Self calibrating clocks for globally asynchronous locally synchronous systems SW Moore, GS Taylor, PA Cunningham, RD Mullins, P Robinson Proceedings 2000 International Conference on Computer Design, 73-78, 2000 | 94 | 2000 |
| Demystifying data-driven and pausible clocking schemes R Mullins, S Moore 13th IEEE International Symposium on Asynchronous Circuits and Systems …, 2007 | 93 | 2007 |
| An energy and performance exploration of network-on-chip architectures A Banerjee, PT Wolkotte, RD Mullins, SW Moore, GJM Smit IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (3), 319-329, 2009 | 90 | 2009 |
| Sponge examples: Energy-latency attacks on neural networks I Shumailov, Y Zhao, D Bates, N Papernot, R Mullins, R Anderson 2021 IEEE European Symposium on Security and Privacy (EuroS&P), 212-231, 2021 | 59 | 2021 |
| Performance analysis of single board computer clusters PJ Basford, SJ Johnston, CS Perkins, T Garnock-Jones, FP Tso, ... Future Generation Computer Systems 102, 278-291, 2020 | 58 | 2020 |
| On the reduction of computational complexity of deep convolutional neural networks P Maji, R Mullins Entropy 20 (4), 305, 2018 | 51 | 2018 |
| To compress or not to compress: Understanding the interactions between adversarial attacks and neural network compression I Shumailov, Y Zhao, R Mullins, R Anderson Proceedings of Machine Learning and Systems 1, 230-240, 2019 | 47 | 2019 |
| Minimising dynamic power consumption in on-chip networks R Mullins 2006 International Symposium on System-on-Chip, 1-4, 2006 | 45 | 2006 |
| Efficient Winograd or Cook-Toom convolution kernel implementation on widely used mobile CPUs P Maji, A Mundy, G Dasika, J Beu, M Mattina, R Mullins 2nd Workshop on Energy Efficient Machine Learning and Cognitive Computing …, 2019 | 34 | 2019 |
| Automatic generation of multi-precision multi-arithmetic CNN accelerators for FPGAs Y Zhao, X Gao, X Guo, J Liu, E Wang, R Mullins, PYK Cheung, ... International Conference on Field Programmable Technology (FPT 2019), 2019 | 33 | 2019 |
| Tagged memory and minion cores in the lowRISC SoC A Bradbury, G Ferris, R Mullins Memo, University of Cambridge, 2014 | 32 | 2014 |
Simon MooreProfessor of Computer Engineering, University of CambridgeVerified email at cl.cam.ac.uk
